History of Quickstart with Xilinx KC705 (No. 1)

• History
• View the diff.
• View the diff current.
• View the source.
• Go to Quickstart with Xilinx KC705.
  • 1 (2020-09-09 (Wed) 05:30:57)

---

OpenFC - an Open FPGA Cluster Toolkit

Prerequisites†

• PC to run Vivado design suite (faster is better, Linux or Windows)
• PC as an FPGA host (Linux x86_64) with a KC705 card

Checking out the source tree†

The source tree is available from our subversion repository:

% svn co https://lut.eee.u-ryukyu.ac.jp/svn/openfc/trunk src

Inside the source tree, there are:

• boards/ : board dependent stuff
• core/ : common stuff (router and misc utilities)
• host/ : host API and software examples
• icap/ : ICAP partial reconfiguration stuff (currently only for Xilinx FPGAs)
• pcie/ : PCI Express DMAC (RIFFA, more DMACs will come soon)
• serdes/ : Serial transceiver stuff (Xilinx Aurora: intel support is planned)
• tcl/ : Tcl scripts to configure projects in FPGA design tools

Hardware setup†

To Prepare FPGA bitstream:

1. Launch Vivado design suite. 2018.3 or later is required.
2. Create a new project. The setup script will override the device selection, so you don't have to choose the correct device part # at this point.
3. Choose Tools -> Run Tcl Script, then open src/tcl/kc705.tcl. Tcl script loads everything you need
   • If your Vivado is newer than 2018.3, open Report -> Report IP status, then check all IPs and do "Upgrade Selected" or you'll get errors on the implementation process.
4. Click "Generate Bitstream," then you'll get a configuration bitstream for the KC705 card.
5. Plug the KC705 board into the host's PCIe slot, power the host&card up, then write bitstream. Using different PCs for Vivado and FPGA host is strongly recommended because we sometimes need to reboot the FPGA host.

This design contains a stream PE that just passes the input stream through.

Driver setup†

You'll need RIFFA driver and libriffa.so (user API library).

% cd src/host/riffa-driver
% make
% sudo make install

And if you want to enable all users to access the FPGA without root privilege, write /etc/udev/rules.d/99-riffa.rules:

KERNEL=="riffa", MODE="777", GROUP="root"

After you reboot the FPGA host, you'll find /dev/riffa.

Run test program†

A stream loopback example is found in src/host .

% cd src/host
% gcc simple-loopback.c fpga-tools-riffa.c fpga-tools.c -lpthread -lriffa
% ./a.out
FDs: o1 xx, o2 xx, i xx
PCIe loopback
done

If any error is found in the returning stream, the values will be dumped on the screen.