Quickstart with Xilinx KC705
Start:
[[OpenFC - an Open FPGA Cluster Toolkit]]
* Prerequisites [#f4bd9d49]
- PC to run Vivado design suite (faster is better, Linux ...
- PC as an FPGA host (Linux x86_64) with a KC705 card
* Step 1: Setup and test the base system [#ffa8234f]
** Checking out the source tree [#iad9c51e]
The source tree is available from our subversion reposito...
% svn co https://lut.eee.u-ryukyu.ac.jp/svn/openfc/trunk...
Inside the source tree, there are:
- boards/ : board dependent stuff
- core/ : common stuff (router and misc utilities)
- host/ : host API and software examples
- icap/ : ICAP partial reconfiguration stuff (currently o...
- pcie/ : PCI Express DMAC (RIFFA, more DMACs will come s...
- serdes/ : Serial transceiver stuff (Xilinx Aurora: inte...
- tcl/ : Tcl scripts to configure projects in FPGA design...
** Hardware setup [#mfbe93bb]
To Prepare FPGA bitstream:
+ Launch Vivado design suite. 2018.3 or later is required.
+ Create a new project. The setup script will override th...
+ Choose Tools -> Run Tcl Script, then open src/tcl/kc705...
#ref(./ip-upgrade.png,right,around,30%);
-- If your Vivado is newer than 2018.3, open Report -> Re...
+ Click "Generate Bitstream," then you'll get a configura...
+ Plug the KC705 board into the host's PCIe slot, power t...
This design contains a stream PE that just passes the inp...
** Driver setup [#cb42811a]
You'll need RIFFA driver and libriffa.so (user API librar...
% cd src/host/riffa-driver
% make
% sudo make install
And if you want to enable all users to access the FPGA wi...
KERNEL=="riffa", MODE="777", GROUP="root"
After you reboot the FPGA host, you'll find /dev/riffa.
** Run test program [#e51cd3b1]
A stream loopback example is found in src/host .
% cd src/host
% gcc simple-loopback.c fpga-tools-riffa.c fpga-tools.c ...
% ./a.out
FDs: o1 xx, o2 xx, i xx
PCIe loopback
done
If any error is found in the returning stream, the values...
* Step 2: Test another Stream PE [#q3426253]
In this step, replace the default "pass" PE that just pas...
+ First, find "pe-pass.v" in the module hierarchy.
#ref(./pe-pass.png,around,right,30%);
-- Both instance and module names are "pe"
-- Right-click and remove the file from project, or just ...
+ Add "pe-intadd.v" to the Vivado project.
-- You can find pe-intadd.v in "pe-base" directory of the...
+ Generate bitstream, program your KC705 card, then reboo...
+ Compile and run the test program
-- Test program is src/host/simple-intadd.c
% gcc simple-intadd.c fpga-tools-riffa.c fpga-tools.c -l...
% ./a.out
FDs: o1 xx, o2 xx, i xx
10000 + 0 = 10000
10001 + 1 = 10001
10002 + 2 = 10002
...
End:
[[OpenFC - an Open FPGA Cluster Toolkit]]
* Prerequisites [#f4bd9d49]
- PC to run Vivado design suite (faster is better, Linux ...
- PC as an FPGA host (Linux x86_64) with a KC705 card
* Step 1: Setup and test the base system [#ffa8234f]
** Checking out the source tree [#iad9c51e]
The source tree is available from our subversion reposito...
% svn co https://lut.eee.u-ryukyu.ac.jp/svn/openfc/trunk...
Inside the source tree, there are:
- boards/ : board dependent stuff
- core/ : common stuff (router and misc utilities)
- host/ : host API and software examples
- icap/ : ICAP partial reconfiguration stuff (currently o...
- pcie/ : PCI Express DMAC (RIFFA, more DMACs will come s...
- serdes/ : Serial transceiver stuff (Xilinx Aurora: inte...
- tcl/ : Tcl scripts to configure projects in FPGA design...
** Hardware setup [#mfbe93bb]
To Prepare FPGA bitstream:
+ Launch Vivado design suite. 2018.3 or later is required.
+ Create a new project. The setup script will override th...
+ Choose Tools -> Run Tcl Script, then open src/tcl/kc705...
#ref(./ip-upgrade.png,right,around,30%);
-- If your Vivado is newer than 2018.3, open Report -> Re...
+ Click "Generate Bitstream," then you'll get a configura...
+ Plug the KC705 board into the host's PCIe slot, power t...
This design contains a stream PE that just passes the inp...
** Driver setup [#cb42811a]
You'll need RIFFA driver and libriffa.so (user API librar...
% cd src/host/riffa-driver
% make
% sudo make install
And if you want to enable all users to access the FPGA wi...
KERNEL=="riffa", MODE="777", GROUP="root"
After you reboot the FPGA host, you'll find /dev/riffa.
** Run test program [#e51cd3b1]
A stream loopback example is found in src/host .
% cd src/host
% gcc simple-loopback.c fpga-tools-riffa.c fpga-tools.c ...
% ./a.out
FDs: o1 xx, o2 xx, i xx
PCIe loopback
done
If any error is found in the returning stream, the values...
* Step 2: Test another Stream PE [#q3426253]
In this step, replace the default "pass" PE that just pas...
+ First, find "pe-pass.v" in the module hierarchy.
#ref(./pe-pass.png,around,right,30%);
-- Both instance and module names are "pe"
-- Right-click and remove the file from project, or just ...
+ Add "pe-intadd.v" to the Vivado project.
-- You can find pe-intadd.v in "pe-base" directory of the...
+ Generate bitstream, program your KC705 card, then reboo...
+ Compile and run the test program
-- Test program is src/host/simple-intadd.c
% gcc simple-intadd.c fpga-tools-riffa.c fpga-tools.c -l...
% ./a.out
FDs: o1 xx, o2 xx, i xx
10000 + 0 = 10000
10001 + 1 = 10001
10002 + 2 = 10002
...
Page:
![[PukiWiki]](image/pukiwiki.png "[PukiWiki]")
