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#author("2023-10-12T07:04:55+00:00","default:osana","osana") #author("2023-10-12T07:05:09+00:00","default:osana","osana") [[OpenFC - an Open FPGA Cluster Toolkit]] * About this project [#n7831f89] This framework provides easy access to: - PCI Express and high-speed (10+Gbps) serial FPGA-to-FPGA interconnect to build an FPGA cluster -- Including Xilinx Aurora-compatible interconnect on Intel FPGAs (coming soon) - User-built accelerators with streaming I/O interface - Stream routing mechanism to allow multiple accelerators also multiple FPGAs - Partial reconfiguration feature to load user modules User-built accelerators can be designed in C++ with Vivado HLS (or Intel HLS) in less board dependent style. The framework also provides an easy-to-use streaming DMA API for host C++ code. ** Recent updates: [#ic4ad42b] - Cyclone/Arria 10 GX Partial Reconfiguration support (Jan. 2022) * Requirements [#x883e32f] - Host PC(s): -- with an FPGA card on its PCI Express slot -- Running Linux (x86_64, kernel 4.x is supported) --- ARM64 Host (ZynqMP SoC) will come soon! - In multi-FPGA use case: -- FPGA cards have to be connected by SFP+ or coaxial cables - To build FPGA design: -- Xilinx FPGAs: Vivado 2018.3 or later -- Intel FPGAs: Quartus Prime Pro 19.1 or later ** Supported FPGA Cards [#zf4d4d4b] Support status of SVN trunk: |FPGA Device| Board |>|>| Feature status|h |~|~| PCIe | Serial Transceiver | Partial Reconf |h |Kintex-7 |[[Xilinx KC705>Boards/Xilinx KC705]] | RIFFA Gen1 x8/XDMA Gen2 x8 | OK | OK | |~| [[Digilent NetFPGA-1G-CML>Boards/Digilent NetFPGA-1G-CML]] | RIFFA Gen2 x4 |~|~| |Kintex Ultrascale |[[Avnet KU040 Dev Board>Boards/Avnet KU040 Dev Board]] | N/A |~|~| |~| Xilinx KCU1500 | XDMA Gen3 x8 |~|Coming soon | |Virtex Ultrascale+ | Xilinx Alveo U50 | XDMA Gen3 x8 |~|~| |Zynq Ultrascale+ | Xilinx ZCU102 (planned) | | | | | Arria 10 GX | Gidel HawkEye-40GP | RIFFA Gen2 x8 | | OK (on trunk) | | Cyclone 10 GX | [[Intel Cyclone 10 GX Dev Board>Boards/Intel Cyclone10 GX Dev Board]] | RIFFA Gen2 x4 | Coming soon | OK (on trunk) | -- More card will be supported. Source code SVN repository: https://lut.eee.u-ryukyu.ac.jp/svn/openfc/ * Documentations [#zac584dd] - [[OpenFC Architecture]] - [[Quickstart with Xilinx KC705]] or Intel Cyclone 10 card - [[Building custom Stream PE with Vivado HLS]] - FPGA Board Porting Guide * Acknowledgements and License [#d1b04ca0] [[RIFFA DMA contoller:https://github.com/KastnerRG/riffa]] is included in this project, with patches to follow-up with the recent version of the Vivado/Quartus design suite and current Linux kernel. RIFFA DMA engine and its driver are provided under the original license. The license of source code (except the RIFFA DMA controller): > "THE BEER-WARE LICENSE" (Revision 42): <yasu@prosou.nu> wrote this file. As long as you retain this notice, you can do whatever you want with this stuff. If we meet someday, and you think this stuff is worth it, you can buy me a beer in return Yasunori Osana at the University of the Ryukyus, Japan.&ref(noname.png); > "THE BEER-WARE LICENSE" (Revision 42): <yasu@prosou.nu> wrote this file. As long as you retain this notice, you can do whatever you want with this stuff. If we meet someday, and you think this stuff is worth it, you can buy me a beer in return Yasunori Osana at the University of the Ryukyus, Japan.
